The present invention relates to a frequency multiplying circuit having a greater multiplying ratio and, in particular, to a circuit having a multiplying ratio of a few thousands of times as great and ensuring less jitter and high stability.
FIG. 11 shows a conventional frequency multiplying circuit using a phase locked loop (PLL) circuit. An oscillation signal Fout output from a voltage controlled oscillator (VCO) 3 is supplied to an input terminal of a frequency divider (DIV) 4. The frequency divider 4 generates a divided signal Fout/N obtained by frequency-dividing the oscillation signal Fout by N. The divided signal Fout/N is supplied to a first input terminal of a phase comparator (PHC) 1. A reference signal Fref is supplied to a second input terminal of a phase comparator 1. The phase comparator 1 produces an error signal Verr corresponding to a phase difference between the divided signal Fout/N and the reference signal Fref. The error signal Verr is supplied to an input terminal of a lowpass filter (LPF) 2. The lowpass filter 2 integrates the error signal Verr and supplies a corresponding DC level output signal Vcont to a control voltage input terminal of the VCO 3.
The operation of the resultant circuit will now be explained below.
If the frequency of the signal Fout/N is lower than that of the reference signal Fref, the phase comparator 1 outputs a low level signal only during a time period in which the phase of the signal Fout/N is delayed behind the reference signal Fref. In the case where a lowpass filter 2 is comprised of an active filter to which negative feedback is applied, the output level of the lowpass filter 2 goes higher than its previous level and the VCO 3 oscillates with a frequency higher than its previous frequency. If the frequency of a divided signal Fout/N of a resultant oscillation signal Fout is lower than that of the reference signal Fref, then the VCO 3 oscillates with a still higher frequency through the same process. If, on the other hand, the frequency of the signal Fout/N goes higher than that of the reference signal Fref, the phase comparator 1 outputs a high level signal only during a time period equal to a phase difference between the divided signal Fout/N and the signal Fref. The corresponding high level pulse is integrated by the lowpass filter 2 and the output level of the lowpass filter 2 goes lower than its previous level. As a result, the VCO 3 oscillates with a frequency lower than its previous oscillation frequency. In this way, comparison is made any plurality of times between the signal Fout/N and the reference signal Fref and a loop operates ceaselessly without producing any phase difference. When the phase difference between the signal Fout/N and the reference signal Fref becomes zero, then the output of the phase comparator 1 becomes a high impedance state and the output of the lowpass filter 2 maintains the same level as its previous level. As a result, the VCO 3 oscillates with the same frequency as its previous oscillation frequency. If such a stable state is reached, then the output frequency Fout of the PLL circuit is given by: EQU Fout=Fref.times.N
where Fref denotes the reference frequency and N the dividing number of the frequency divider 4.
Further, if use is made of a frequency divider 4 having a programmable counter, the dividing number N becomes variable and it is possible to obtain any output frequency Fout with the frequency Fref as a unit. However, the output of the phase comparator 1 is normally produced in synchronism with the rise or fall of the reference frequency Fref. In consequence, when the multiplying ratio between the output frequency Fout and the reference frequency Fref becomes greater, a time interval from the outputting of the error signal from the phase comparator to that of the next error signal becomes longer from the standpoint of the output frequency Fout. As a result, the PLL circuit is not adequately controlled and the stability of the output frequency Fout is lowered. The extent of stability is evaluated by the phase error showing a phase shift between the reference signal Fref and the output signal Fout as well as the jitter representing a disturbance between the clocks of the output signal Fout. If, normally, the output amplitude of the lowpass filter 2 becomes greater in the PLL circuit, the phase error becomes smaller but the jitter becomes prominent. On the other hand, if the output amplitude of the lowpass filter becomes smaller, the phase error becomes greater but the jitter becomes smaller.
If the frequency of the reference signal Fref is constant, the greatest value of the multiplying ratio N of the PLL circuit is determined by the greatest oscillable frequency Fout of the VCO 3. In order to increase the multiplying ratio N, it is necessary to increase the greatest value of the VCO's output frequency Fout. This means increasing a conversion efficiency Kf (=Fout/Vcont) of the VCO 3. If, however, the conversion efficiency Kf becomes greater, the output frequency Fout of the VCO 3 varies greater when the control voltage Vcont varies due to, for example, noise. It has, therefore, been difficult to accurately control the VCO 3.
The ordinary VCO, even performing frequency control, never controls the duty ratio of the clock waveform of the output signal Fout. In the case where it is necessary to ensure 50% as the duty ratio of the clock waveform, a circuit as shown in FIG. 12 is used. Here, the same reference numerals are employed to designate parts or elements corresponding to those shown above and any further explanation is, therefore, omitted. In FIG. 12, a VCO 3 oscillates with double the frequency required. The output terminal of the VCO 3 is connected to the input terminal of a divide-by-2 frequency divider 8 and the output terminal of the frequency divider 8 is connected to the input terminal of a frequency divider 4. The output signal of the frequency divider 8 becomes a clock signal whose duty ratio is 50%. Since, in this case, the conversion efficiency Kf of the VCO 3 becomes still greater, it becomes difficult to control the VCO 3.
Further, if the multiplying ratio N of the PLL circuit becomes greater, a reference frequency Fref of the PLL circuit, being compared with an output frequency Fout of the VCO 3, becomes a considerably low one. When the reference frequency Fref becomes a lower one, the control period of a phase comparator 1 for controlling the VCO 3 becomes longer, thus making it difficult to accurately control the VCO 3.
In the case where the PLL circuit is built on an LSI chip, it is necessary to provide a margin two to three times the lock range required, taking that process variation into consideration. It is, therefore, difficult, in practice, to increase the stability of the PLL circuit by lowering the conversion coefficient of the VCO.
Further, the multiplier suffers a greater influence from noise from other circuits on the chip, such as a digital circuit system in particular to the PLL circuit. It is thus difficult to operate the PLL circuit stably.
If, in this way, the multiplying ratio N of the PLL circuit becomes greater, the stability of the oscillation frequency is lowered, resulting in a lowering in the phase error characteristic as well as in a jitter characteristic.